A Disciplined Approach to the Development of Platform Architectures

ion, and thus more compact specification. It also directly provides support for VLIW compilers in terms of clear description of instruction level parallelism. MAD and Expression are similar in their goals of providing support for simulators and compilers for VLIW processors. However, MAD has less redundancy in the description and thus fewer issues of consistency in description. 6.3 Liberty Simulator Specification There are two steps to generating a simulator. First, a view generator converts a MAD Description into a Liberty Simulator Specification (LSS). Then, using this specification, the Liberty Simulation Environment (LSE) constructs a simulator by instantiating microarchitectural modules and connecting them with instantiated channels. A module is a microarchitectural component template, which interacts with other parts of the simulator via input and output ports. A channel is a communication template, which connects one or more module ports. In general, modules describe significant functionality such as caches, branch predictors, and functional units while channels describe timing interactions using notions such as wire, queue, and filter. The LSS directs the instantiation and connection of the module and channel templates. The Liberty Simulator Specification serves two purposes. First, LSS is a Liberty simulator view of the architecture LSS represents the microarchitecture in a manner conducive to simulator generation. Second, LSS allows the designer to directly manipulate the microarchitecture to be modeled. This access is necessary for modeling irregularities introduced by VLSI constraints or other details not describable with MAD. Unlike MAD, LSS approximates the computer architect's view of the microarchitecture modules and channels generally have a physical counterpart in the hardware. The relative ease of manipulating the LSS makes customizing a simulator to match a candidate microarchitecture an efficient process for the microarchitect. Like MAD, LSS is stored as an XML ASCII description, but typically a graphical visualizer is the preferred user interface. A complete Liberty Simulator Specification consists of four parts: module instantiations to create architectural functions, channel instantiations to create connections, control points to specify complex or non-local control not implied by channel connections, and event instantiations to provide the user or compiler with performance feedback. Module Instantiation. To create an architectural component in the simulator, a module instantiation is indicated in LSS using the instantiation directive, INST. In Figure 2, an instruction fetch unit ifetch1 is created from the ifetch template. Each instantiated module can have its behavior customized via parameters. Module instantiation tools use these parameters at simulator construction time to create code appropriate for the specific case. All module types define a default set of parameters to use if a parameter is not specified in LSS. Here the default ifetch parameter decode_latency is overridden in ifetch1 to have a value of 1 cycle. Channel Instantiation and Connection. Channels are instantiated much like modules they have parameters and are derived from a channel type template. In Figure 2, a queue named pred_chan is created between the instruction fetch (fetch1) lookup port and the branch predictor (bpred1) predict port to initiate branch predictions at the appropriate time. In this example, the channel uses the default type parameters. Data passing through channels has the type specified by datatype. Here, the channel only relays a trigger signal without associated data. Control Points and Exported State. Channel connections imply local and regular control information. For example, instruction fetch initiates branch predictions with the pred_chan channel. Unfortunately, channels cannot express all control possible in real machines, so a control point mechanism exists to express this nonlocal or irregular control logic. In Figure 2, the control function decide_to_fetch stops instruction fetch whenever the rename logic has fewer than 8 free registers. To accomplish this, the control function uses the free_regs exported state function from the rename1 instantiated module in making a